Index: sys/dev/ic/dwc_eqos.c =================================================================== RCS file: /cvsroot/src/sys/dev/ic/dwc_eqos.c,v retrieving revision 1.44 diff -p -u -r1.44 dwc_eqos.c --- sys/dev/ic/dwc_eqos.c 28 May 2026 09:33:30 -0000 1.44 +++ sys/dev/ic/dwc_eqos.c 30 May 2026 09:18:42 -0000 @@ -139,15 +139,13 @@ eqos_mii_readreg(device_t dev, int phy, GMAC_MAC_MDIO_ADDRESS_GOC_READ | GMAC_MAC_MDIO_ADDRESS_GB; WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); - delay(10000); - for (retry = MII_BUSY_RETRY; retry > 0; retry--) { + delay(10); addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { *val = RD4(sc, GMAC_MAC_MDIO_DATA) & 0xFFFF; break; } - delay(10); } if (retry == 0) { device_printf(dev, "phy read timeout, phy=%d reg=%d\n", @@ -173,14 +171,12 @@ eqos_mii_writereg(device_t dev, int phy, GMAC_MAC_MDIO_ADDRESS_GOC_WRITE | GMAC_MAC_MDIO_ADDRESS_GB; WR4(sc, GMAC_MAC_MDIO_ADDRESS, addr); - delay(10000); - for (retry = MII_BUSY_RETRY; retry > 0; retry--) { + delay(10); addr = RD4(sc, GMAC_MAC_MDIO_ADDRESS); if ((addr & GMAC_MAC_MDIO_ADDRESS_GB) == 0) { break; } - delay(10); } if (retry == 0) { device_printf(dev, "phy write timeout, phy=%d reg=%d\n", @@ -441,6 +437,7 @@ eqos_alloc_mbufcl(struct eqos_softc *sc) m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); if (m != NULL) m->m_pkthdr.len = m->m_len = m->m_ext.ext_size; + MCLAIM(m, &sc->sc_ec.ec_rx_mowner); return m; } @@ -503,33 +500,58 @@ eqos_setup_rxfilter(struct eqos_softc *s EQOS_ASSERT_LOCKED(sc); pfil = RD4(sc, GMAC_MAC_PACKET_FILTER); + + /* turn off promiscous mode */ + /* turn off the receive-all mode */ + /* turn off the non-UDP/TCP filter */ + /* turn off broadcast filter */ + /* turn off pass all multicast mode */ + /* turn on hash or perfect mode */ + /* turn off source address filter */ + /* turn off inverse source address filter */ + /* turn off inverse destination address filter */ + /* turn off multicast hash table matching */ + /* turn off unicast hash table matching */ + /* XXX keep IP Layer3+4 filter */ + /* XXX keep VLAN tag filter */ + /* don't pass control packets */ pfil &= ~(GMAC_MAC_PACKET_FILTER_PR | + GMAC_MAC_PACKET_FILTER_RA | + GMAC_MAC_PACKET_FILTER_DNTU | + GMAC_MAC_PACKET_FILTER_DBF | GMAC_MAC_PACKET_FILTER_PM | + GMAC_MAC_PACKET_FILTER_SAF | + GMAC_MAC_PACKET_FILTER_SAIF | + GMAC_MAC_PACKET_FILTER_DAIF | GMAC_MAC_PACKET_FILTER_HMC | - GMAC_MAC_PACKET_FILTER_PCF_MASK); - hash[0] = hash[1] = ~0U; + GMAC_MAC_PACKET_FILTER_HUC | + GMAC_MAC_PACKET_FILTER_PCF_MASK); + pfil |= GMAC_MAC_PACKET_FILTER_HPF; ETHER_LOCK(ec); if ((sc->sc_if_flags & IFF_PROMISC) != 0) { ec->ec_flags |= ETHER_F_ALLMULTI; - pfil |= GMAC_MAC_PACKET_FILTER_PR | - GMAC_MAC_PACKET_FILTER_PCF_ALL; + /* enable promiscous mode */ + pfil |= GMAC_MAC_PACKET_FILTER_PR; + /* also receive control packets */ + pfil |= GMAC_MAC_PACKET_FILTER_PCF_ALL; + /* ignored */ + hash[0] = hash[1] = ~0U; } else { - pfil |= GMAC_MAC_PACKET_FILTER_HMC; - hash[0] = hash[1] = 0; + hash[0] = hash[1] = 0U; ec->ec_flags &= ~ETHER_F_ALLMULTI; + /* enable multicast hash table matching */ + pfil |= GMAC_MAC_PACKET_FILTER_HMC; ETHER_FIRST_MULTI(step, ec, enm); while (enm != NULL) { if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN) != 0) { - ec->ec_flags |= ETHER_F_ALLMULTI; + /* disable multicast hash table matching */ pfil &= ~GMAC_MAC_PACKET_FILTER_HMC; + /* pass all multicast instead */ pfil |= GMAC_MAC_PACKET_FILTER_PM; - /* - * Shouldn't matter if we clear HMC but - * let's avoid using different values. - */ - hash[0] = hash[1] = 0xffffffff; + /* ignored */ + hash[0] = hash[1] = ~0U; break; } crc = ether_crc32_le(enm->enm_addrlo, ETHER_ADDR_LEN); @@ -545,13 +567,16 @@ eqos_setup_rxfilter(struct eqos_softc *s /* Write our unicast address */ eaddr = CLLADDR(ifp->if_sadl); - val = eaddr[4] | (eaddr[5] << 8) | GMAC_MAC_ADDRESS0_HIGH_AE; + val = eaddr[4] | (eaddr[5] << 8); + val = __SHIFTIN(val, GMAC_MAC_ADDRESS_HIGH_ADDR) + | GMAC_MAC_ADDRESS_HIGH_AE; WR4(sc, GMAC_MAC_ADDRESS0_HIGH, val); val = eaddr[0] | (eaddr[1] << 8) | (eaddr[2] << 16) | (eaddr[3] << 24); WR4(sc, GMAC_MAC_ADDRESS0_LOW, val); /* Multicast hash filters */ + /* XXX assumes 64 bit hashtable size */ WR4(sc, GMAC_MAC_HASH_TABLE_REG0, hash[0]); WR4(sc, GMAC_MAC_HASH_TABLE_REG1, hash[1]); @@ -621,8 +646,11 @@ eqos_init_locked(struct eqos_softc *sc) EQOS_ASSERT_LOCKED(sc); EQOS_ASSERT_TXLOCKED(sc); - if ((ifp->if_flags & IFF_RUNNING) != 0) + if ((ifp->if_flags & IFF_RUNNING) != 0) { + /* Only Setup RX filter */ + eqos_setup_rxfilter(sc); return 0; + } /* Setup TX/RX rings */ eqos_init_rings(sc, 0); @@ -827,6 +855,9 @@ eqos_rxintr(struct eqos_softc *sc, int q m0 = sc->sc_rx_receiving_m; mprev = sc->sc_rx_receiving_m_last; + DPRINTF(EDEB_INTR, "qid: %u, discarding %u, m0 %p\n", + qid, discarding, m0); + for (index = sc->sc_rx.cur; ; index = RX_NEXT(index)) { eqos_dma_sync(sc, sc->sc_rx.desc_map, index, index + 1, RX_DESC_COUNT, @@ -1322,17 +1353,16 @@ eqos_get_eaddr(struct eqos_softc *sc, ui } maclo = RD4(sc, GMAC_MAC_ADDRESS0_LOW); - machi = RD4(sc, GMAC_MAC_ADDRESS0_HIGH) & 0xFFFF; - if ((maclo & 0x00000001) != 0) { - aprint_error_dev(sc->sc_dev, - "Wrong MAC address. Clearing the multicast bit.\n"); - maclo &= ~0x00000001; - } - + machi = __SHIFTOUT(RD4(sc, GMAC_MAC_ADDRESS0_HIGH), + GMAC_MAC_ADDRESS_HIGH_ADDR); if (maclo == 0xFFFFFFFF && machi == 0xFFFF) { /* Create one */ - maclo = 0x00f2 | (cprng_strong32() & 0xffff0000); + maclo = 0x00f2 | (cprng_strong32() << 16); machi = cprng_strong32() & 0xffff; + } else if (maclo & 0x00000001) { + aprint_error_dev(sc->sc_dev, + "Wrong MAC address. Clearing the multicast bit.\n"); + maclo &= ~0x00000001; } eaddr[0] = maclo & 0xff; @@ -1443,7 +1473,8 @@ eqos_setup_dma(struct eqos_softc *sc, in sc->sc_tx.queued = TX_DESC_COUNT; for (i = 0; i < TX_DESC_COUNT; i++) { error = bus_dmamap_create(sc->sc_dmat, EQOS_TXDMA_SIZE, - TX_MAX_SEGS, MCLBYTES, 0, BUS_DMA_WAITOK, + TX_MAX_SEGS, MCLBYTES, 0, + BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &sc->sc_tx.buf_map[i].map); if (error != 0) { device_printf(sc->sc_dev, @@ -1483,7 +1514,8 @@ eqos_setup_dma(struct eqos_softc *sc, in for (i = 0; i < RX_DESC_COUNT; i++) { error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, - RX_DESC_COUNT, MCLBYTES, 0, BUS_DMA_WAITOK, + RX_DESC_COUNT, MCLBYTES, 0, + BUS_DMA_WAITOK | BUS_DMA_ALLOCNOW, &sc->sc_rx.buf_map[i].map); if (error != 0) { device_printf(sc->sc_dev, Index: sys/dev/ic/dwc_eqos_reg.h =================================================================== RCS file: /cvsroot/src/sys/dev/ic/dwc_eqos_reg.h,v retrieving revision 1.11 diff -p -u -r1.11 dwc_eqos_reg.h --- sys/dev/ic/dwc_eqos_reg.h 28 May 2026 09:33:30 -0000 1.11 +++ sys/dev/ic/dwc_eqos_reg.h 30 May 2026 09:18:42 -0000 @@ -47,11 +47,21 @@ #define GMAC_MAC_CONFIGURATION_RE (1U << 0) #define GMAC_MAC_EXT_CONFIGURATION 0x0004 #define GMAC_MAC_PACKET_FILTER 0x0008 +#define GMAC_MAC_PACKET_FILTER_RA (1U << 31) +#define GMAC_MAC_PACKET_FILTER_DNTU (1U << 21) +#define GMAC_MAC_PACKET_FILTER_IPFE (1U << 20) +#define GMAC_MAC_PACKET_FILTER_VTFE (1U << 16) #define GMAC_MAC_PACKET_FILTER_HPF (1U << 10) +#define GMAC_MAC_PACKET_FILTER_SAF (1U << 9) +#define GMAC_MAC_PACKET_FILTER_SAIF (1U << 8) #define GMAC_MAC_PACKET_FILTER_PCF_MASK (3U << 6) +#define GMAC_MAC_PACKET_FILTER_PCF_NOCTL (0U << 6) +#define GMAC_MAC_PACKET_FILTER_PCF_CTL (1U << 6) #define GMAC_MAC_PACKET_FILTER_PCF_ALL (2U << 6) +#define GMAC_MAC_PACKET_FILTER_PCF_MATCH (3U << 6) #define GMAC_MAC_PACKET_FILTER_DBF (1U << 5) #define GMAC_MAC_PACKET_FILTER_PM (1U << 4) +#define GMAC_MAC_PACKET_FILTER_DAIF (1U << 3) #define GMAC_MAC_PACKET_FILTER_HMC (1U << 2) #define GMAC_MAC_PACKET_FILTER_HUC (1U << 1) #define GMAC_MAC_PACKET_FILTER_PR (1U << 0) @@ -93,11 +103,18 @@ #define GMAC_MAC_VERSION_SNPSVER_MASK 0xFFU #define GMAC_MAC_DEBUG 0x0114 #define GMAC_MAC_HW_FEATURE(n) (0x011C + 0x4 * (n)) +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ __BITS(25,24) +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_0 0 +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_64 1 +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_128 2 +#define GMAC_MAC_HW_FEATURE1_HASHTBLSZ_256 3 #define GMAC_MAC_HW_FEATURE1_TXFIFOSIZE __BITS(10,6) #define GMAC_MAC_HW_FEATURE1_RXFIFOSIZE __BITS(4,0) #define GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT 14 #define GMAC_MAC_HW_FEATURE1_ADDR64_MASK (0x3U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) #define GMAC_MAC_HW_FEATURE1_ADDR64_32BIT (0x0U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) +#define GMAC_MAC_HW_FEATURE1_ADDR64_40BIT (0x1U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) +#define GMAC_MAC_HW_FEATURE1_ADDR64_48BIT (0x2U << GMAC_MAC_HW_FEATURE1_ADDR64_SHIFT) #define GMAC_MAC_MDIO_ADDRESS 0x0200 #define GMAC_MAC_MDIO_ADDRESS_PA_SHIFT 21 #define GMAC_MAC_MDIO_ADDRESS_RDA_SHIFT 16 @@ -122,6 +139,17 @@ #define GMAC_MAC_ADDRESS0_HIGH 0x0300 #define GMAC_MAC_ADDRESS0_HIGH_AE (1U << 31) #define GMAC_MAC_ADDRESS0_LOW 0x0304 +#define GMAC_MAC_ADDRESS1_HIGH 0x0308 +#define GMAC_MAC_ADDRESS1_LOW 0x030c +#define GMAC_MAC_ADDRESS2_HIGH 0x0310 +#define GMAC_MAC_ADDRESS2_LOW 0x0314 +#define GMAC_MAC_ADDRESS3_HIGH 0x0314 +#define GMAC_MAC_ADDRESS3_LOW 0x031c +#define GMAC_MAC_ADDRESS_HIGH_AE __BIT(31) +#define GMAC_MAC_ADDRESS_HIGH_SE __BIT(30) +#define GMAC_MAC_ADDRESS_HIGH_MB __BITS(29,24) +#define GMAC_MAC_ADDRESS_HIGH_DCS __BIT(16) +#define GMAC_MAC_ADDRESS_HIGH_ADDR __BITS(15,0) #define GMAC_MMC_CONTROL 0x0700 #define GMAC_MMC_CONTROL_UCDBC (1U << 8) #define GMAC_MMC_CONTROL_CNTPRSTLVL (1U << 5) Index: sys/dev/acpi/eqos_acpi.c =================================================================== RCS file: /cvsroot/src/sys/dev/acpi/eqos_acpi.c,v retrieving revision 1.2 diff -p -u -r1.2 eqos_acpi.c --- sys/dev/acpi/eqos_acpi.c 24 Dec 2023 16:12:54 -0000 1.2 +++ sys/dev/acpi/eqos_acpi.c 30 May 2026 09:18:42 -0000 @@ -114,7 +114,8 @@ eqos_acpi_attach(device_t parent, device } sc->sc_dmat = BUS_DMA_TAG_VALID(aa->aa_dmat64) ? aa->aa_dmat64 : aa->aa_dmat; - sc->sc_phy_id = MII_PHY_ANY; + // sc->sc_phy_id = MII_PHY_ANY; + sc->sc_phy_id = 0; sc->sc_csr_clock = CSR_RATE_RGMII; eqos_acpi_init_props(sc, handle); @@ -140,10 +141,8 @@ eqos_acpi_init_props(struct eqos_softc * prop_dictionary_t prop = device_properties(sc->sc_dev); ACPI_STATUS rv; ACPI_INTEGER ival; -#if notyet ACPI_HANDLE axi; char *sval; -#endif /* Defaults */ prop_dictionary_set_uint(prop, "snps,wr_osr_lmt", 4); @@ -159,7 +158,6 @@ eqos_acpi_init_props(struct eqos_softc * prop_dictionary_set_bool(prop, "snps,tso", true); } -#if notyet rv = acpi_dsd_string(handle, "snps,axi-config", &sval); if (ACPI_SUCCESS(rv)) { rv = AcpiGetHandle(handle, sval, &axi); @@ -177,5 +175,4 @@ eqos_acpi_init_props(struct eqos_softc * } kmem_strfree(sval); } -#endif }